Charge redistribution analog-to-digital converters are widely used to convert analog signals into binary digital representations. These converters sample an analog voltage signal and convert the analog signal to digital code. Charge redistribution analog-to-digital converters generally consist of a binarily-weighted array of capacitors connected to a comparator. Often, the comparator is comprised of a series of differential-type or inverter-type amplifiers. Charge redistribution analog-to-digital converters utilize successive approximation register (SAR) logic to set three-state switches connected to the bottom plates of the capacitors in the capacitor array. The three states for the three-state switches are a connection to the input voltage, a connection to ground potential, and a connection to a reference voltage. The top plates of the capacitors in the capacitor array are connected together to form one node which is the top plate of the capacitor array.
A problem common to charge redistribution analog-to-digital converters is a voltage offset which affects the output voltage of the comparator. This voltage offset can cause inaccurate conversions of the analog signal to digital code. Eliminating this voltage offset from a charge redistribution analog-to-digital converter can consume a relatively large amount of time. In some cases, the time consumed can be as large as the time consumed during the conversion process.